Chemical Sensors; Neural Interfaces; Electronic Circuit Clocking; Circuit Design; High Performance Microprocessors; Mixed Signal Microprocessors; Biomedical Implants.
Chemical Sensors: (H. Goldberg, M. Ger, H. Cantor, G.S. Cha*, R. Hower, S. Martin, S. Joo*, K. Campbell)
Prof. Brown started working in the area of solid-state liquid chemical sensors in his own Ph.D. research at the University of Utah. Under the direction of Prof. Robert Huber, with Jiri Janata as a very involved member of his committee, he developed a miniature silicon-based chemical sensor array with on-chip electronics. In this project, he developed a junction-isolated NMOS semiconductor process and designed an eight-ion-sensor array using ionophore-doped polymeric membranes, in which the signal from each sensor electrode was buffered by an integrated operational amplifier. This first-of-a-kind smart chemical sensor included digital control circuitry and an analog multiplexor which reduced the number of interface connections needed to seven, which fit on the narrow (1.4 mm) end of the rectangular sensor chip. The junction isolation allowed the sensor chip to be used in solution with only the bond-wire end of the chip encapsulated. The use of integrated electronics improved the signal to noise ratio by more than three orders of magnitude, and facilitated the concurrent use of multiple sensors selective to different chemicals. This chip generated all of the data needed to implement chemometrics techniques for reducing errors due to imperfect selectivity of the ionophore-based transducers.
As a faculty member at the University of Michigan, Prof. Brown, with his students, continued to solve the fundamental problems in solid-state chemical sensors. They optimized ion-selective membranes for all of the simple ions based on polyurethane and silicone matrices that had vastly improved biocompatibility and adhesion to the substrate compared to the commonly-used PVC. They developed mass fabrication processes that yielded membranes having precisely controlled dimensions and electrochemical characteristics. They developed a Silicon-on-Insulator (SOI) semiconductor process to give intrinsic encapsulation to these devices that must operate in conductive solution without shorting high impedance signals to the solution. Throughout the sensor research, novel packaging approaches were developed. The SOI process included a p-i-n photodiode that was used to implement an optically-coupled sensor for detecting alcohol and other non-ionic species. A smart sensor chip was fabricated in this SOI process that included an analog multiplexor, a programmable gain amplifier, a 12-bit analog-to-digital converter, digital control circuitry, and a standard serial interface to a computer -- the whole instrument was on the sensor chip.
Solid-state conductivity sensors were developed for quantifying hematocrit levels and the ionic strengths of other fluids. Enzymatically- and immunologically-coupled sensors were demonstrated. Amperometric sensors were developed for detecting and determining the concentrations of neurochemicals (dopamine, serotonin, acetylcholine), heavy metals (arsenic, lead), and any of a host of other molecules that have well-defined redox potentials which lie within the water window. With stripping voltammetry, these sensors were able to detect Arsenic at levels as low as 0.3 parts per billion. These sensors were also integrated with electronics, this time using commercially processed CMOS circuits as the substrate; post-processing steps developed in Prof. Brown’s lab were employed to form the sensors on top of the circuitry. A model of the full sensor/electronics system was developed to evaluate the noise and optimize the sensor and circuit design. One of the circuits developed and integrated with the sensor was a fully differential potentiostat, which doubled the effective voltage swing available for driving the redox reactions, thereby allowing the electronics to be implemented in modern, fine-featured, low-voltage semiconductor processes. Multiple sensor types were merged onto the same chip to achieve a wide range of sensing capabilities.
With a portfolio of patents generated from this work, Prof. Brown was involved in founding two companies, i-SENS and Sensicore, which commercialized the solid-state sensor technology. i-SENS, headquartered in Seoul, Korea, manufactures and markets glucose sensors and glucometers throughout the world. It has a capacity to make 1B sensors per year in a new factory in Wonju City, Korea. The company has also developed a bed-side blood gas and electrolyte instrument that will soon be manufactured in a new factory in the Incheon Free Economic Zone. Sensicore, founded in Ann Arbor, MI, focused on water sensing with a hand-held instrument based upon a single silicon sensor chip that quantifies 18 components/parameters of clean water. The company had more than $30M of venture capital, and was sold to GE Water and Process Technologies in April of 2008.
Since being back at the University of Utah, Prof. Brown and his group, with Profs. Cha and Nam from Kwangwoon University, have developed several novel reference electrodes that can be miniaturized to sizes comparable to those of the sensors. Working with Prof. Henry White’s team in Chemistry, they developed the world’s smallest man-made potentiometric sensor, a nanopore-based device that was used as a scanning chemical microscope to plot the ion flux passing through an opening the size of a human skin pore. Prof. Brown’s group has developed silicon-based nanopore sensors that can be mass-fabricated with varying, well-controlled pore sizes. The devices have metal electrodes in isolated cavities behind the nanopores. These structures will be the basis of nano-potentiometric sensors, nano-amperometric sensors, and nano particle sizers/counters. The isolated cavities with independent Pt and IrOx electrodes will make possible the concurrent operation of these various sensor types in an array, including multiple particle counters having different size ranges, and concurrently counting particles of opposite polarity. Such a device will find many applications in environmental water and air quality testing, national security applications, and nano- and bio-technology research.
Neural Interfaces: (H. Cantor, T. Strong, R. Franklin, S. Kellis)
Prof. Brown’s work in neural sensors started as an effort to apply his group’s chemical sensing technology to silicon-based brain probes which, at that time, detected only electrical signals. Communication between neurons happens, of course, through both electrical and chemical means, so adding the ability to identify and quantify the neurochemical concentrations in the vicinity of a neuron, along with the electrical spikes, could greatly enhance the understanding of neuron behavior. Their first design was a silicon-based, microfabricated, passive, in vitro array organized in a 4 x 4 pattern, in which each sensor used an electrode for sensing the action potential, and with other electrodes formed a voltammetric sensor for monitoring neurochemicals. Five versions of this array were made, with electrode sizes ranging from 2 to 100 mm. The sensor array was packaged in a ceramic integrated circuit pin grid array package with lead wires encapsulated, and a small cloning chamber cemented to the sensor chip surface. Human stem cells (hNT cell line from Stratagene) were plated onto the surface over an appropriate matrix, and cultured into neurons. Neurons from this cell line produce spontaneous electrical activity, and secrete acetylcholine and dopamine. Calibration curves for dopamine taken in culture media indicated detection limits for dopamine below 100nM. Neuroelectrical and neurochemical recordings were taken on 24 cell cultures over 75 days. Action potential propagation from neuron to neuron was evident in the data. Electrical spikes and chemical response were correlated in many instances. A cell behavior known as potentiation, in which a neuron fires to prime or activate a particular neural pathway was exhibited in the data; a succeeding pulse causes a larger reaction because of the initial priming. The capture of such events, with multiple action potential spikes in rapid succession followed by a large release of neurotransmitter, highlights the capability of the devices for use in studying the interdependence of neuroelectrical and neurochemical behaviors. This was, to our knowledge, the first case of recording such data without external stimulation. A complete computer model of the sensor’s electrochemical behavior was developed for use in optimizing interface electronics. To improve signal fidelity, CMOS potentiostats were integrated into the sensor using the post-processing approach mentioned in the Chemical Sensors section above.
After returning to Utah, Prof. Brown and his students implemented their neurosensors as in vivo brain probes that could concurrently detect neurochemical and electrophysiological signals. They studied various materials as they sought a biocompatible reference electrode for neuroprobes, and eventually developed an activated Iridium Oxide Film electrode with excellent characteristics for use in sensing neurochemicals. Silicon needle probes were designed with Pt and IrOx electrodes on the same shank in appropriate configurations for concurrently measuring local field potentials, action potentials, and neurochemical concentrations. The probes were coated with the perfluorinated ion-exchange resin Nafion to improve selectivity of the platinum sites to more than 100:1 for dopamine over interfering species. The multi-modal probes were implanted in the striatum of urethane-anesthetized rats to examine reciprocal influences of amperometry on neuronal activity, and spatiotemporal characteristics of dopamine effluence vs. local field potential and spike activity following electrical stimulation of the medial forebrain bundle (MFB). The utility of these probes for neuroscience studies was demonstrated as extra-synaptic dopamine overflow in the striatum was correlated with local field potentials and electrical spike activity, driven by the frequency and amplitude of electrical stimulation of the MFB. These probes are now being made available commercially through NeuroNexus Technologies, Ann Arbor, MI, a company founded by Prof. Brown’s collaborator, Daryl Kipke.
Chronic implantation of neural probes is problematic because as the probes move in the soft brain tissue, they see signals from different neurons, necessitating constant retraining of the decoder. Furthermore, biology tries to encapsulate the foreign body, insulating its sensing electrodes from the signals. To achieve better chronic performance of a brain-machine interface, Prof. Brown and his student, Spencer Kellis, in conjunction with neurosurgeon Paul House and Bradley Greger in Bioengineering, have experimented with tiny (40 mm micro electrocorticographic or ECoG) electrodes placed on the surface of the brain. Experiments were conducted to determine whether non-penetrating, high-density microwire electrodes could provide sufficient information to serve as the interface for decoding motor cortical signals. These electrode arrays were implanted over the motor cortex in epilepsy patients who performed reaching movements with a computer mouse while data were recorded. The whole array of 16 electrodes fits in the area normally occupied by a single standard ECoG electrode. It was learned that the electrodes are capable of recording predominantly linearly-independent data if placed 2mm or more apart. Signals from cortical columns, sensed by the micro ECoG electrodes, were filtered into frequency ranges, and the amount of power in each band was monitored. Principle component analysis of the filtered and binned data was used to distinguish between the two movements. The gamma band power at 30-40 Hz increased substantially beginning 500 mS before movement in the contralateral direction; movements in the ipsilateral direction corresponded to a general attenuation in power over the gamma band. The algorithm was able to predict with good accuracy which direction the patient was going to move his arm. While the studies to date involved movement of the arm, the inter-electrode spacing was designed to allow for the decoding of individual finger and hand movements, hopefully enabling the dextrous intuitive control of a prosthetic arm and hand. More detailed studies using both hand and arm movement tasks and more sophisticated decode paradigms will be needed to validate the applications of the non-penetrating electrode arrays. The group’s latest sensing accomplishment, first reported at the Society for Neuroscience meeting October 18, 2009, is the first differentiation of spoken words using non-penetrating electrodes. Their hope is that this technology will lead to an option for locked-in patients to communicate. Prof. Brown’s group is developing a low-power mixed-signal microprocessor to serve as an implanted interface to micro ECoG arrays (see below).
Electronic Circuit Clocking: (P. Stetson, A. Drake, F. Gebara, M. McCorquodale, N. Gaskin)
All synchronous digital systems employ a clock to pace the operation of the circuit. In modern integrated circuits, the clock design has a major effect on both the speed and power dissipation of the circuit. Prof. Brown’s group has contributed in several ways to improved integrated circuit clocking. In the mid 1990s, as microprocessors became faster than the clocks that could be distributed on printed circuit boards, phase-locked loops, which multiply the clock frequency, became necessary on-chip modules. The group designed CMOS and Complementary Gallium Arsenide (CGaAs) digital phase-locked loops and delay-locked loops (which align the phase but do not change the frequency) that employed current-steering logic and novel low-voltage circuit techniques to achieve the best phase noise results for a given operating voltage reported to that date. This work included a new simulation technique for analyzing phase jitter. As microprocessor clock frequencies continued to rise, there was a need for ever faster phase-locked loops. Prof. Brown’s group developed a new class of oscillators based on an efficient NOR-gate interpolator. Oscillator frequencies as high as 4.6 GHz were achieved in a 0.18 μm CMOS process, with a 3X tuning range and rms jitter values as low as 0.87ps. The group also experimented with a resonant clock distribution system, the first to use the parasitic wiring and gate capacitance of the clock tree as the resonant capacitance in a monolithic harmonic clock oscillator. A method for characterizing the affects of circuit data flow on jitter in both standard and resonant clocks was developed, including a method of extracting the jitter contribution caused by data from time-domain and frequency-domain stability measurements.
While designing a commercial microprocessor as a consulting project, Prof. Brown learned that the quartz crystal oscillators typically used as the time-base for digital systems sometimes cost more than the microprocessor they support. The idea was conceived to develop an all-silicon clock generator that could be integrated right onto the microprocessor, replacing the off-chip crystal and passive devices required to implement a crystal oscillator. The researchers evaluated a number of options, and settled on a harmonic oscillator with on-chip inductors and capacitors, and extensive compensation circuitry for temperature and voltage variation. This introduced an entirely new approach to clocking microprocessors. Instead of starting with a stable lower-frequency clock and scaling it up with a phase-locked loop, they generated a very high frequency clock and divided it down to the desired frequency. The crystal-derived clock is very clean because of the crystal’s high Q; the harmonic oscillator’s output is not as good in terms of jitter and stability. But just as noise worsens as the square root of the multiplier in a phase-locked loop, it improves as the square root of the divisor in these circuits, yielding a high quality clock at the desired frequency. The research involved developing sacrificial under-etching to maximize the on-chip inductor’s Q with no added masks or processing steps, so the oscillator could be fabricated in standard, advanced CMOS processes. The project included a great deal of theoretical noise analysis, and some correction of commonly accepted theory. Major contributions included novel analog circuitry to stabilize the frequency over voltage, temperature and device parameters; fast initial tuning techniques; and packaging solutions to avoid humidity sensitivity. Significant contributions were also made in design methodology for mixed technology (digital, analog, RF and MEMS) systems on chips, and a CAD tool called Newton for MEMS device design has been licensed to a third party. The resulting all-silicon harmonic oscillator can be integrated onto a microprocessor or other circuit, entirely eliminating the need for a crystal oscillator. These all-silicon oscillators have the unique characteristic that they reach stability within as little as 20 nS after power is applied, compared to hundreds of mS for a phase-locked-loop to reach stability. This makes practical fine-grained power cycling to reduce power dissipation, a feature that is particularly valuable for extending battery life in portable or implanted electronics. They are smaller, lower-power, more robust physically, and lower cost than crystal oscillators or MEMS resonant oscillators.
Prof. Brown and his student, Michael McCorquodale, founded Mobius Microsystems to commercialize all-silicon harmonic oscillators. Integrated versions of the oscillators are in volume production on USB interface chips, and discrete versions are being sold as pin-for-pin replacements for motherboard clocks and as bare die to be bonded into a package with the primary IC, forming a system-in-a-package solution that makes the part self-clocked. The monolithic CMOS harmonic oscillators appear to be a disruptive technology that could have broad impact on the electronics industry. Top-tier Silicon Valley VCs have invested more than $20M in the company to date. New applications in a number of product sectors are developing as the frequency accuracy and jitter are continually improved; the latest parts are accurate to within 20 ppm over the commercial temperature and voltage range. Prof. Brown’s group integrates these clocks onto the embedded microprocessors that they design, and they are exploring new applications for the basic technology, ranging from ultra-wideband radio transmitters to sensors.
Circuit Design: (K. Wu, P. Parakh, C. Gauthier, K. Das, R. Rao, J. Sivagnaname, M. Guthaus, A. Ghosh)
The design of circuits underpins all of the areas addressed by Prof. Brown’s research group, so there is overlap between some of the activities in this and the other sections.
Prof. Brown’s group and researchers from the GE Corporate Research and Development Center significantly raised the operating temperatures of bulk CMOS circuits by using a thin epi substrate, increasing doping levels, and using refractory metal for interconnect. They increased 300C latchup holding voltage by 4X and holding current by 30X over an equivalent bulk CMOS process. High-temperature design rules were developed that assured latchup-free operation at 200C. A transistor model that accurately represented the space charge at high temperatures (by solving the Poisson's equation and two-carriers' current continuity equations instead of assuming the depletion layer approximation) provided insights into circuit operation at very high temperatures. For example, it became clear that silicon circuits can never operate at high speeds and high temperatures because, in addition to the mobility degradation, the small-signal capacitance equivalent depletion-layer width becomes very small at high temperatures, significantly increasing the parasitic capacitive load.
While microprocessor clock speeds increased during the 1990s at a rate of about 40% per year, off-chip signaling rates improved more slowly, at about 14% per year. Concurrently, the number of transistors on chips increased according to Moore’s Law (doubling about every 18 months) but the number of package pins increased at only about 12% per year. Despite the development of more latency-tolerant architectures (multi-level caches, prefetching, stream buffers, etc.), these effects led to a significant bandwidth bottleneck between processor chips and off-chip memory. Prof. Brown’s group developed a switched-current transceiver with an active current mirror receiver that achieved Gb/s/pin operation in a 0.5 mm CMOS process (current technology at that time). This cascoded switched-current signaling architecture was also implemented in CGaAs and compared to Gunning Transceiver Logic, large-buffer voltage signaling, and differential signaling. The switched-current interface was found to be four times more power efficient than similar source-synchronous interfaces.
Prof. Brown pioneered the use of commercial CAD tools in university courses and research, but when a design automation capability they needed was not available in the commercial tool suites, his group sometimes developed it, always building on top of the best available commercial tools and making the new tools compatible with commercial tool flows. Examples of such contributions were the tools for high-performance gallium arsenide (GaAs) circuits and multichip modules. They developed circuit design techniques and CAD tools that guaranteed process tolerance in the circuits; SRAM compilers that optimize the design for the desired power-delay product; a tool that optimally places modules on a datapath; an automatic block placement tool that minimizes routing congestion; an area-I/O place and route tool for flip-chip packaging; and software that guides engineers through the cost-benefit analysis for nonlinear process scaling. On a sabbatical, Prof. Brown worked with Cascade Design Automation to develop a commercial GaAs circuit compiler that incorporated many of these capabilities. In work that was related to clocking, statistical design, and process parameter variation, his group developed a CMOS clock tree optimizer that correlated both clock and data-path parametric sensitivities to make designs more robust. A quadratic programming heuristic was introduced that was able to realize this improvement without sacrificing deterministic skew. The resulting trees have an average improvement of 16.3% in expected skew with the addition of only 2% to clock power. In a project aimed at making the performance of synthesized circuits approach that of custom circuits, the team developed a logical-effort-based transistor sizing tool, coupled to a cell synthesizer that generated physical, logical and simulation views (years before commercial tools offered this capability), and datapath tiling for wirelength minimization and predictable loads. The on-the-fly library generator enabled studies of circuit performance vs. library size. When the group needed embedded benchmark programs that were not readily available, they developed and published the MiBench suite, which is now widely used in industry and academia for benchmarking embedded processor architectures. According to Google, the original paper has been cited 953 times, and there are more than 22,000 references to it on the internet. Prof. Brown’s group saw a need for a library of digital and analog circuit modules that university students could use in class and research projects, so they developed the University of Michigan Intellectual Property Source (UMIPS), and populated it with circuits from their own projects. This resource facilitated collaboration and the reuse of circuits, so that designers could focus on the modules that were unique to their projects. Users from around the world have tapped this resource.
Working closely with the IBM Research Labs, Prof. Brown and his students developed circuit techniques for partially-depleted (PD) and fully-depleted (FD) Silicon-on-Insulator (SOI) technologies. Most of this work had a theme of reducing power dissipation at a given circuit speed. Prof. Brown spent a sabbatical focused on low-power circuits in SOI in the Exploratory VLSI group of the IBM Austin Research Laboratory just before moving to the University of Utah. Because of SOI’s superior short channel effects and better scalability, devices of the future will implement some form of SOI (planar, Tri-Gate, FinFET). As semiconductor process dimensions and film thicknesses have been scaled, subthreshold source-drain leakage and gate-source leakage have increased to the point that the leakage power in ICs threatened to exceed dynamic power dissipation. New gate insulators and other process techniques are important parts of the solution, but good circuit techniques are also critical. Prof. Brown’s group developed circuits that mitigate the parasitic bipolar effect and timing uncertainty in PD SOI. They studied and refined multi-threshold CMOS (MTCMOS) for PD SOI, improving the gate delay by as much as 45% and the standby leakage by a factor of eight. Similar techniques were shown to be effective in dynamic logic, as well. Design automation tools were developed to guide the design of SOI circuits and implement the new circuit techniques. An optimal header/footer tapering algorithm was developed for FD SOI; it reduced standby leakage by a factor of 20 over that of conventional MTCMOS. A dynamic logic scheme for FD SOI circuits was developed that reduces leakage power by a factor of 10 to 30 while speeding up the circuits by 15% over a conventional domino logic scheme. All of the new techniques were evaluated in terms of their effects on power rail bounce. Prof. Brown’s group was first to study power-performance trade-offs of SOI circuits taking gate leakage into consideration. CAD tools for efficiently estimating gate leakage were developed, and efficient methods for determining the lowest-leakage data vectors to be applied to static combinational circuits in standby mode were developed. Circuit reorganization schemes were developed for both static and dynamic circuits that reduced gate leakage by 75% and total leakage by 40%. Power dissipation in data buses was reduced through the development of skewed pulse buses, which achieved a 20% reduction in active mode leakage, an order of magnitude reduction in standby leakage, and a delay improvement of 20%. Leakage was studied as a function of process parameter variation, and a model was developed for determining the optimal supply voltage for parametric yield optimization. Analog circuits in SOI, such as a body-compensated current mirror that is stable in the presence of gate leakage, and comparators that employ offset cancellation through body biasing, were also designed, fabricated and tested.
In light of the emergence of SOI technologies and effects that have come with aggressive scaling of electronic devices (short channel non-idealities and leakage), Prof. Brown’s group took a fresh look at unipolar logic families, using datapath blocks from their PowerPC-architecture PUMA Processor for realistic evaluations. They showed that pseudo-nMOS circuits could reduce standby leakage current by a factor of five, and that these circuits could be designed closer to the maximum performance point, since the load bias can be easily adjusted to compensate for process parameter variability. They also developed two variants of dynamic logic, controlled-load limited switch dynamic logic, and hybrid limited switch dynamic logic, which offer better immunity to noise and charge sharing than basic LSDL. Wide implementations of CL-LSDL were shown to reduce power by as much as 50% over conventional CL-LSDL circuits, and H-LSDL improved delay by 30% over basic CL-LSDL. These logic styles are well-suited for high clock rate, high switching activity circuits such as digital signal processors, memory decoders and datapath circuits, and they can be freely mixed with other logic styles.
Among the greatest challenges in modern semiconductor technologies, where the gate oxide is only a few atoms thick and edge roughness of physical features makes a significant difference in transistor dimensions, is the variability of device parameters. Prof. Brown’s group has developed a technique for detecting parameter variation and compensating for it, so that circuits can be designed for the desired operating point, rather than needing to be over-designed to tolerate large parameter variations. Other detection schemes are based purely on a representative circuit’s delay; they function properly only if the parameter variations of the p- and n-transistors are shifted in the same direction. The approach developed in Prof. Brown’s group uses delay, but also considers rise and fall times of signals in the representative circuit, thereby providing independent information on parametric shifts in the NMOS and PMOS transistors. With this information, the overall circuit speed can be adjusted by tuning the power supply voltage, and the gain for each transistor type can be adjusted independently using substrate bias to drive the operating point back to the desired position. This detection and compensation approach is in fact a low-power circuit technique because it minimizes the power wasted in designing circuits that will operate with broad parameter variation, and it balances the gain of the p- and n-transistors, forcing the circuit to the most efficient operating point. This technique for forcing transistors to the optimal operating point may be even more useful in analog circuits than in digital circuits. The approach has also been successfully employed by Prof. Brown’s group to monitor PMOS devices for negative bias temperature instability and to compensate for this transistor-aging phenomenon. As in all of the research in Prof. Brown’s group, the circuits are not only designed and simulated, but are also fabricated, tested, and demonstrated in realistic applications.
High Performance Microprocessors: (J. Dykstra, A. Chandna, T. Huff, M. Upton, T. Basso, S. Gold)
The late 1980s and early 1990s were times of exploration of various semiconductor technologies for the fabrication of microprocessors. With DARPA funding, Prof. Brown’s high-speed circuits group designed three gallium arsenide microprocessors in E/D MESFET technology, three in CMOS, and one in complementary heterostructure-insulated-gate FET technology (CGaAs). Prof. Brown was a proponent of holistic design and multilevel optimization; the research group’s activities covered many facets of high-performance processor design, including process technology, circuit design, packaging, CAD tools, architecture, and the architecture’s relationship to software compilers. In 1993, they presented at the International Solid-State Circuits Conference, a MIPS-architecture GaAs microprocessor that operated at speeds as high as 200 MHz with 24W power dissipation. That clock speed was exceeded only by an ECL processor presented at the same conference, which was clocked at 300 MHz, but dissipated 115W. Close working relationships developed between this university group and Vitesse Semiconductor, Motorola, MIPS Computer Systems, Cray Computer, Tera Computer, IBM, Green Hills Software, and Cascade Design Automation. The results of their exploration of very large-scale digital circuits in GaAs influenced technology directions taken by Vitesse and Motorola, and paved the way for Tera Computers to build a GaAs supercomputer.
Prof. Brown’s group developed a number of MESFET circuits which demonstrated novel ideas at the gate level (e.g., the patented current-mirror memory cell and power-rail logic); module level (e.g., high-speed modified Ling adder); and microarchitecture level (e.g., decoupled superscalar architecture and partially-decoded instruction cache). They were the first group to implement dynamic circuits in complementary GaAs. They also contributed to advanced packaging technologies for high performance computing (multichip modules, fine-pitch flip- chip gold bonding, and area-array I/O). They optimized the PowerPC microarchitecture for implementation in a small transistor-budget, and demonstrated a radiation-hard CGaAs microprocessor that operated at 86 MHz and 2W. Prof. Brown’s research group has been seen as one of only a few at universities that has the capability and facilities to prototype modern microprocessors.
Mixed Signal Microprocessors: (K. Kraver, F. Gebara, R. Senger, E. Marsman, N. Gaskin, B. Redd)
Working with colleagues at Michigan, Prof. Brown brought his sensor and integrated circuit research areas together through the design of the MS-8 mixed-signal microprocessor which served as a single-chip interface instrument for the solid-state chemical and physical sensors that he and others have developed. The MS-8 included voltage, current and capacitive inputs, an accurate on-chip temperature sensor, an analog multiplexor, bandgap voltage reference, programmable-gain instrumentation amplifier, SD analog-to-digital converter, a complete 8-bit microprocessor, on-chip memory, a 16x16 multiply 40-bit accumulate MAC for signal processing, a variety of counters/timers, and serial and parallel I/O modules. The microprocessor instruction set and modified Harvard architecture were original to this project and aimed at sensor-interface needs; they included bit test and set instructions, a fast interrupt response with 32 priority levels, and ultra-lite direct memory access. It was fabricated in a 0.35 mm digital process.
Prof. Brown was one of five faculty members, led by Ken Wise, at the University of Michigan, who wrote the proposal for the Michigan Wireless Integrated Microsystems Engineering Research Center. This ERC proposal, focused on microsystems for remote environmental sensor and biomedical implant applications, referenced the MS-8 as evidence that the proposers could implement fully integrated systems. Prof. Brown was the thrust leader for Micropower Circuits in the ERC until he moved to become Dean of Engineering at the University of Utah. He has continued to be fully involved in the Center, participating in weekly administrative meetings (by video conference), industrial advisory board meetings, retreats, and annual reviews.
Low power circuits have been a focus of the ERC, since both of its testbeds require operation on battery power. Three microprocessors have been designed in the WIMS series. They share a 16-bit RISC architecture with a 3-stage pipeline and windowed register file that was designed from a clean sheet of paper, on-chip memory, a loop cache, several peripheral communication interfaces, and the all-silicon harmonic oscillator described above. Efficient methods were developed for measuring the energy expended in the execution of each instruction, and a power-aware C compiler that uses this information was developed for the WIMS instruction set architecture by Prof. Scott Mahlke’s group at Michigan; feedback from the compiler studies was used to optimize the architecture. The Gen 1 processor, implemented in a 180 nm CMOS technology, was aimed at remote environmental sensing applications. It incorporated a full analog front-end that pushed the limits of low-voltage, low-power analog design in advanced digital processes. The nominal process operating voltage was 1.8 V; to accommodate the voltage change as a single battery cell falls from fully charged to its end-of-life potential, the analog circuits were designed to operate on any voltage between 1.8 V and 900 mV. Weak inversion biasing was used extensively to reduce the need for voltage headroom, to reduce transistor noise and power, and to increase amplifier gain. A second-order SD modulator was employed on this chip. When driving a 10 kW, 150 pF load, the opamp achieves a DC gain of 80 dB, a unity gain frequency greater than 1.3 MHz, and a phase margin of 60°; the opamp draws a quiescent current of 128 mA. The sub-1 V SD modulator is enabled by a dynamically biased pseudo-differential integrator. This integrator supports low-voltage operation by employing the reset-opamp technique, thus avoiding the need for high-swing switches. Correlated double sampling curtails the effects of 1/f noise, a more serious problem in fine-featured processes.
Gen 2, also implemented in a 180 nm CMOS process, was designed as an implantable cochlear prosthesis controller. In addition to the processor core, memory and peripherals, it includes a digital signal processor block consisting primarily of cascaded 1st, 6th and 4th order infinite impulse response filters that implement the Continuous Interleaved Sampling Algorithm used to drive the electrodes in cochlear prostheses. To provide the required flexibility for patient fitting, all filter coefficients were made programmable by the processor. This chip included clock gating, the ability to modify the clock speed dynamically, and the ability to employ different clocks in the core and in the DSP. Prof. Brown’s group took the lead in implementing the cochlear prosthesis testbed, integrating the Gen 2 processor, application software, and chips designed by other WIMS researchers into the demonstration system.
The Gen 3 processor is being designed in a 65 nm CMOS process to address brain machine interface needs. It will include the processor, all-silicon clock generator, memory, hardware DSP functionality, an analog front-end customized for neural signals, and an ultra-wideband wireless interface. This version of the processor adds DMA instructions to efficiently move blocks of data or machine state to and from memory. Test chips implementing most of the modules have been fabricated and tested. The fully-functional microprocessor core dissipates 350 mW running at 10 MHz or 10 mW running at 100 MHz.