PIERRE-EMMANUEL GAILLARDON portrait
  • Adjunct Associate Professor, School Of Computing
  • Professor, Elect & Computer Engineering
  • Associate Professor, Elect & Computer Engineering
801-585-3422

Publications

  • A. Boston, R. Gauchi, P.-E. Gaillardon, "Secure eFPGA Configuration: A System-Level Approach", ARC 2024, Aveiro, Portugal, March 2024. Published, 03/2024.
  • P. Cadareanu, P.-E. Gaillardon, "A Process Tuning Analysis for the Three-Independent-Gate Field-Effect Transistor," IEEE Nanotechnology Materials and Devices Conference (NMDC), Salerno, Italy, Oct. 2023. Published, 10/2023.
  • G. Brown, G. Gore, P.-E. Gaillardon, “Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 20-23 June 2023, Foz de Iguacu, Brazil. Published, 06/2023.
  • J. Bhandari, A. Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, R. Karri., "Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 20-23 June 2023, Foz de Iguacu, Brazil. Published, 06/2023.
  • A. Arora, A. Bhamburkar, A. Borda, T. Anand, R. Sehgal, B. Hanindhito, P.-E. Gaillardon, J. Kulkarni, L. John, “CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration,” IEEE Transactions on Reconfigurable Technology and Systems (TRETS), June 2023. Published, 06/2023.
  • G. Gore, X. Tang, P.-E. Gaillardon, "A Scalable and Area Efficient Configuration Circuitry for Semi-Custom FPGA Design", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), April 2023. Published, 04/2023.
  • A. Alacchi, E. Giacomin, R. Gauchi, S. Kulis, P. -E. Gaillardon, "Smart-Redundancy with In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), April 2023. Published, 04/2023.
  • D. How, T. Ansell, V. Betz, C. Lavin, T. Speers, P.-E. Gaillardon, "Open-source and FPGAs: Hardware, Software, Both or None?," 31st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 13-14 February 2023, Monterey, CA, USA. Published, 02/2023.
  • A. Alacchi, P.-E. Gaillardon, "Low Latency SEU Detection in FPGA CRAM with In-Memory ECC Checking", IEEE Transactions on Circuits and Systems I, January 2023. Published, 01/2023.
  • W. Lau Neto, Y. Li, P.-E. Gaillardon, C. Yu, "End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit", Transactions on Computer-Aided Design of Integrated Circuits and System", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022. Published, 10/2022.
  • M. Keyser, R. Gauchi, P. -E. Gaillardon, "An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing," 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), Oct 3-5, 2022, Patras, Greece. Published, 10/2022.
  • A. Alacchi, P. -E. Gaillardon, "Programmable Local Clock SET Filtering for SEE-Resistant FPGA," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3879-3883, Sept. 2022. Published, 09/2022.
  • T. Becnel, K. Kelly and P.-E. Gaillardon, "Tiny Time-Series Transformers: Realtime Multi-Target Sensor Inference At The Edge," 2022 IEEE International Conference on Omni-layer Intelligent Systems (COINS), August 8-10, 2022, Barcelona, Spain. Published, 08/2022.
  • A. Snelgrove, N. Crawford-Taylor, S. Temple, P.-E. Gaillardon, Timing Driven Resynthesis for Open Source Tools, IWLS 2022, July 18-21 2022, Virtual. Published, 07/2022.
  • C. Muscari Tomajoli, L. Collini, J. Bhandari, A. K. T. Moosa, B. Tan, X. Tang, P.-E. Gaillardon, R. Karri, C. Pilato, "ALICE: An Automatic Design Flow for eFPGA Redaction", DAC, July 10-14, 2022, San Francisco, CA, USA. Published, 07/2022.
  • W. Lau Neto, L. Amaru, V. Possani, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, "Improving LUT-Based Optimization for ASIC", DAC, July 10-14, 2022, San Francisco, CA, USA. Published, 07/2022.
  • R. Gauchi, A. Snelgrove , P.-E. Gaillardon, "An Open-Source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis", IEEE International Symposium of Circuits and Systems (ISCAS), May 28-June 1 2022, Austin, TX, USA. Published, 06/2022.
  • A. Snelgrove, P.-E. Gaillardon, "Programmable logic elements using multigate ambipolar transistors", 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 6-8 2022, Prague, Czech Republic. Published, 04/2022.
  • G. Ammes, W. Lau Neto, P. Butzen, P.-E. Gaillardon, R. Ribas, "A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal", Transactions on Computer-Aided Design of Integrated Circuits and System, Jan 2022. Published, 01/2022.
  • E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, P.-E. Gaillardon, " 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs," VLSI-SoC: Design Trends, Springer International Publishing, 2021. Published, 12/2021.
  • E. Giacomin, S. Gudaparthi, J. Boemmels, R. Balasubramonian, F. Catthoor, P.-E. Gaillardon, "A Multiply-And-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow", IEEE Transactions on Nanotechnologies, vol.20, pp 873-882, December 2021. Published, 12/2021.
  • W. Lau Neto, M. Trevisan Moreira, Y. Li, L. Amaru, C. Yu, P.-E. Gaillardon, "SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping," 58th Design Automation Conference (DAC), 5-9 December 2021, San Francisco, CA, USA. Published, 12/2021.
  • M. Thammasack, G. De Micheli, P.-E. Gaillardon, "Effect of O2- migration in Pt/HfO2/Ti/Pt structure," Resistive Switching: Oxide Materials, Mechanisms, Devices and Operations (Ed.: Rupp, Jennifer, Ielmini, Daniele, Valov, Ilia), Electronic Materials: Science & Technology, 2021. Published, 12/2021.
  • S. Temple, A. Snelgrove, W. Lau Neto, P.-E. Gaillardon, "LSOracle 2.0: Capabilities, Integration, and Performance", Workshop on Open-Source EDA Technology (WOSET), November 4, Virtual. Published, 11/2021.
  • J. Bhandari, A. Khader, T. Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, "Exploring eFPGA-based Redaction for IP Protection", ICCAD, 1-4 November 2021. Published, 11/2021.
  • K. Kelly, A. Butterfield, E. Xing, K. Le, T. Sayahi, J. Moore, T. Becnel, M. Meyer, R. Whitaker, P.-E. Gaillardon, "Building an Aerosol Sensing Sensor Network and Inspiring Citizen Scientists", AAAR Conference, 18-22 October, 2021. Published, 10/2021.
  • M. Couriol, E. Giacomin, P.-E. Gaillardon, "A 12 pA Sigma Delta ADC Topology for Chemiresistive Sensor-Based Application", VLSI-Soc, 4-8 Octobre 2021. Published, 10/2021.
  • M. Couriol, P. Cadareanu, E. Giacomin, P.-E. Gaillardon, "A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors", VLSI-Soc, 4-8 Octobre 2021. Published, 10/2021.
  • P. Cadareanu, P.-E. Gaillardon, "A TCAD Simulation Study of Three-Independent-Gate Field-Effect Transistors at the 10-nm Node," IEEE Transactions on Electron Devices, vol. 68, no. 8, pp. 4129-4135, August 2021. Published, 08/2021.
  • A. Snelgrove, S. Temple, P.-E. Gaillardon, "Structure Aware Partitioning for Mixed LogicSynthesis", IWLS, 19-21 July, 2021, Virtual. Published, 07/2021.
  • W. Lau Neto, M. Trevisan Moreira, Y. Li, L. Amaru, C. Yu, P.-E. Gaillardon, "A Supervised Learning Approach for Technology Mapping", IWLS, 19-21 July, 2021, Virtual. Published, 07/2021.
  • G. Brown, V. Tenace, P.E. Gaillardon, "NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks", ASAP, 7-8 July, 2021, Virtual. Published, 07/2021.
  • E. Giacomin, F. Catthoor, P.-E. Gaillardon, "Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow," IEEE International Symposium on Circuits and Systems (ISCAS), 23-26 May 2021, Daegu, Korea. Published, 05/2021.
  • A. Alacchi, E. Giacomin, X. Tang, P.-E. Gaillardon, "Smart-Redundancy: an Alternative SEU/Set Mitigation Method for FPGAs," IEEE International Symposium on Circuits and Systems (ISCAS), 23-26 May 2021, Daegu, Korea. Published, 05/2021.
  • P. Cadareanu, J. Romero-Gonzalez, P.E. Gaillardon, "Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors", IEEE Journal of the Electron Devices Society, pp. 1-9, April 2021. Published, 04/2021.
  • S. Reda, L. Stok, P.-E. Gaillardon, "Guest Editors’ Introduction: The Resurgence of Open-Source EDA Technology", IEEE Design &Test, vol. 38(2), April 2021. Published, 04/2021.
  • G. Gore, X. Tang, P.-E. Gaillardon, "A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs," International Symposium on Physical Design (ISPD), 21-24 March 2021, Virtual. Published, 03/2021.
  • S. Temple, W. Lau Neto, M. Austin, X. Tang, P.-E. Gaillardon, "LSOracle: Open-source Mixed Logic Synthesis", Invited Paper, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 29-April 1, 2021, Virtual. Published, 03/2021.
  • T. Becnel, P.-E. Gaillardon, "A Deep Learning Approach of Sensor Fusion Inference at the Edge," Design, Automation and Test in Europe (DATE), 1-5 February 2021, Virtual. Published, 02/2021.
  • S. Rai, W. Lau Neto, Y. Miyasaka, X. Zhang, M. Yu, Q. Y. M. Fujita, G. B. Manske, M. F. Pontes, L. S. da Rosa Junior, M. S. de Aguiar, P. F. Butzen, P.-C. Chien, Y.-S. Huang, H.-R. Wang, J.-H. R. Jiang, J. Gu, Z. Zhao, Z. Jiang, D. Z. Pan, B. A. de Abreu, I. S. Campos, A. Berndt, C. Meinhardt, J. T. Carvalho, M. Grellert, S. Bampi, A. Lohana, A. Kumar, W. Zeng, A. Davoodi, R. O. Topaloglu, Y. Zhou, J. Dotzel, Y. Zhang, H. Wang, Z. Zhang, V. Tenace, P.-E. Gaillardon, A. Mishchenko, S. Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization," Design, Automation and Test in Europe (DATE), 1-5 February 2021, Virtual. Published, 02/2021.
  • K. Kelly, W. Xing, T. Sayahi, L. Mitchell, T. Becnel, P.-E. Gaillardon, M. Meyer, R. Whitaker, "Community-Based Measurements Reveal Unseen Differences during Air Pollution Episode," Environmental Science & Technology, vol. 55, 1, pp. 120-128, January 2021. Published, 01/2021.
  • A. Eliahu, R. Ronen, P.-E. Gaillardon, and S. Kvatinsky, "multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-Low-Power Architectures", ACM Journal on Emerging Technologies in Computing Systems, Accepted for publication. Published, 01/2021.
  • W. Lau Neto, M. Trevisan Moreira, L. Amaru, C. Yu, P.-E. Gaillardon, "Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization," 26nd Asia and South Pacific Design Automation Conference (ASP-DAC), 18-21 January 2021, Tokyo, Japan. Published, 01/2021.
  • J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, P.-E. Gaillardon, "Accelerating Inference on Binary Neural Networks with Digital RRAM Processing," VLSI-SoC: New Technology Enabler, pp 257-278, Springer International Publishing, 2020. Published, 12/2020.
  • P. Cadareanu, G. Gore, E. Giacomin, P.-E. Gaillardon, "A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors," VLSI-SoC: New Technology Enabler, pp 307-322, Springer International Publishing, 2020. Published, 12/2020.
  • T. Sayahi, A. Garff, T. Quah, K. Le, T. Becnel, K. Powell, P.-E. Gaillardon, A. Butterfield, K. Kelly, "Long-term Calibration Models to Estimate Ozone Concentrations with a Metal Oxide Sensor," Environmental Pollution, vol. 267, 115363, December 2020. Published, 12/2020.
  • E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, P.-E. Gaillardon, G. De Micheli, "Extending Boolean Methods for Scalable Logic Synthesis," IEEE Access, vol. 8, pp. 226828-226844, December 2020. Published, 12/2020.
  • S. Temple, W. Lau Neto, M. Austin, X. Tang, P.-E. Gaillardon, "LSOracle: Using Mixed Logic Synthesis in an Open Source ASIC Design Flow," Workshop on Open-Source EDA Technology, 2020 (WOSET), 5 November 2020, Virtual. Honorable mention for best contribution award. Honorable mention for best video award. Published, 11/2020.
  • X. Tang, G. Gore, E. Giacomin, A. Alacchi, B. Chauviere, P.-E. Gaillardon, "OpenFPGA: Towards Automated Prototyping for Versatile FPGAs," Workshop on Open-Source EDA Technology, 2020 (WOSET), 5 November 2020, Virtual. Best contribution award. Honorable mention for best video award.. Published, 11/2020.
  • D. Mallia, A. Kochanski, K. Kelly, R. Whitaker, W. Xing, L. Mitchell, A. Jacques, A. Farguell, J. Mandel, P.-E. Gaillardon, T. Becnel, S. Krueger, "Evaluating Wildfire Smoke Transport Within a Coupled Fire‐Atmosphere Model Using a High‐Density Observation Network for an Episodic Smoke Event Along Utah's Wasatch Front," Journal of Geophysical Research: Atmospheres, vol. 125, no. 20, October 2020. Published, 10/2020.
  • E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, P.-E. Gaillardon, "Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow," 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 5-7 October 2020, Salt Lake City, UT, USA. Published, 10/2020.
  • X. Tang, E. Giacomin, A. Alacchi, B. Chauviere, P.-E. Gaillardon, "OpenFPGA: An Opensource Framework for Agile Prototyping Customizable FPGAs", IEEE Micro, vol. 40, no. 4 , pp. 41-48, July/August 2020. Published, 08/2020.
  • C. Mullen, T. W. Collins, W. Xing, R. Whitaker, T. Sayahi, T. Becnel, P. Goffin, P.-E. Gaillardon, M. Meyer, K. E Kelly, "Patterns of distributive environmental inequity under different PM2.5 air pollution scenarios for Salt Lake County public schools", Environmental Research, Volume 186, July 2020, 109543. Published, 07/2020.
  • J. Moore, K. Kelly, K. My Quyen, P. Goffin, A. Butterfield, J. Wiese, T. Becnel, M. Dailey, P.-E. Gaillardon, “Engaging Pre-College Students in Hypothesis Generation using a Citizen Scientist Network of Air Quality Sensors,” 2020 ASEE Annual Conference & Exposition, 21-24 June 2020, Montreal, UT, Canada. Published, 06/2020.
  • W. Lau Neto, V. Possani, F. Marranghello, J. Matos, P.-E. Gaillardon, A. Reis, R.P. Ribas, "Exact Benchmark Circuits for Logic Synthesis," IEEE Design & Test, vol. 37, no. 3 , pp. 51-58, June 2020. Published, 06/2020.
  • S. Narayanan, K. Taht, R. Balasubramonian, E. Giacomin, P.-E. Gaillardon, "An Architecture and Dataflow Tailored for Spiking Neural Networks," 47th International Symposium on Computer Architecture (ISCA), May 30 - June 4, Valencia, Spain. Published, 05/2020.
  • M. Austin, W. Lau Neto, S. Temple, L. Amaru, X. Tang, P.-E. Gaillardon, “A Scalable Mixed Synthesis Framework for Heterogeneous Networks,” Design, Automation and Test in Europe (DATE), Interactive presentation, 9-13 March 2020, Grenoble, France. Published, 03/2020.
  • D. Vana, P.-E. Gaillardon, A. Teman, “C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors,” IEEE Transactions on Nanotechnology, vol. 19, no. 1, pp. 123-136, January 2020. Published, 01/2020.
  • J. Reuben, N. Talati, N. Wald, R. Ben-Hur, A. Haj Ali, P.-E. Gaillardon, "A Taxonomy and Evaluation Framework for Memristive Logic," Handbook of Memristor Networks, Springer, pp. 1065-1099, 2019. Published, 12/2019.
  • D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Memory Effects in Multi-Terminal solid state devices and their Applications," Handbook of Memristor Networks, Springer, pp. 1021-1064, 2019. Published, 12/2019.
  • X. Tang, E. Giacomin, A. Alacchi, P.-E. Gaillardon, “A Study on Switch Block Patterns for Tileable FPGA Routing Architectures,” 2019 International Conference on Field Programmable Technology, 9-13 December 2019, Tianjin, China. Published, 12/2019.
  • T. Sayahi, D. Kaufman, T. Becnel, K. Kaur, A. Butterfield, S. Collingwood, Y. Zhang, P.-E. Gaillardon, K. Kelly, "Development of a calibration chamber to evaluate the performance of low-cost particulate matter sensors," Environmental Pollution, vol. 255, pp. 932-940, December 2019. Published, 12/2019.
  • T. Becnel, K. Tingey, J. Whitaker, T. Sayahi, K. Le, P. Goffin, A. Butterfield, K. Kelly, P.-E. Gaillardon, “A Distributed Low-Cost Pollution Monitoring Platform,” IEEE Internet of Things Journal. vol. 6, no. 6, pp. 10738-10748, December 2019. Published, 12/2019.
  • W. Lau Neto, M. Austin, S. Temple, L. Amaru, X. Tang, P.-E. Gaillardon, “LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence,” Invited paper, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 4-7 November 2019, Westminster, CO, USA. Published, 11/2019.
  • P. Cadareanu, P.-E. Gaillardon, “Nanoscale Three-Independent-Gate Transistors: Geometric TCAD Simulations at the 10 nm-Node,” IEEE Nanotechnology Materials Devices Conference, 27-30 October 2019, Stockholm, Sweden. Published, 10/2019.
  • A. Nag, C.N. Ramachandra, R. Balasubramonian, R. Stutsman, E. Giacomin, H. Kambalasubramanyam, P.-E. Gaillardon, “GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment,” 52nd IEEE/ACM International Symposium on Microarchitecture, 12-16 October 2019, Columbus, OH, USA. Published, 10/2019.
  • S. Gudaparthi, S. Narayanan, R. Balasubramonian, E. Giacomin, H. Kambalasubramanyam, P.-E. Gaillardon, “Wire-Aware Architecture and Dataflow for CNN Accelerators,” 52nd IEEE/ACM International Symposium on Microarchitecture, 12-16 October 2019, Columbus, OH, USA. Published, 10/2019.
  • J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, P.-E. Gaillardon, “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories,” 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6-9 October 2019, Cusco, Peru. Published, 10/2019.
  • G. Gore, P. Cadareanu, E. Giacomin, P.-E. Gaillardon, “A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors,” 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6-9 October 2019, Cusco, Peru. Published, 10/2019.
  • X. Tang, E. Giacomin, A. Alacchi, B. Chauvière, P.-E. Gaillardon, “OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs,” 29th International Conference on Field Programmable Logic and Applications (FPL), 9-13 September 2019, Barcelona, Spain. Published, 09/2019.
  • W. Lau Neto, X. Tang, M. Austin, L. Amarú, P.-E. Gaillardon, “Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 15-17 July 2019, Miami, FL, USA. Published, 07/2019.
  • G. Resta, A. Leonhardt, Y. Belaji, S. De Gendt, P.-E. Gaillardon, G. De Micheli, “Devices and Circuits using Novel 2-Dimensional Materials: a Perspective for Future VLSI Systems,” IEEE Transactions on Very Large Scale Integration Systems. vol. 27, no. 7, pp. 1486-1503, July 2019. Published, 07/2019.
  • T. Becnel, T. Sayahi, K. Kelly, P.-E. Gaillardon, "A Recursive Least Squares Approach to Partially Blind Calibration of a Pollution Sensor Network," 15th IEEE International Conference on Embedded Software and Systems (ICESS), 2-3 June 2019, Las Vegas, NV, USA. Published, 06/2019.
  • M. Austin, W. Lau Neto, L. Amarú, X. Tang, P.-E. Gaillardon, “Towards a Novel Logic Synthesis Framework Supervised by Convolutional Neural Network,” 28th International Workshop on Logic & Synthesis (IWLS), 21-23 June 2019, Lausanne, Switzerland. Published, 06/2019.
  • W. Lau Neto, X. Tang, M. Austin, L. Amarú, P.-E. Gaillardon, “Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs,” 28th International Workshop on Logic & Synthesis (IWLS), 21-23 June 2019, Lausanne, Switzerland. Published, 06/2019.
  • T. Greenberg-Toledo, E. Giacomin, S. Kvatinsky, P.-E. Gaillardon, “A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications,” TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan. Published, 05/2019.
  • X. Tang, E. Giacomin, Natan Chetrit, P.-E. Gaillardon, “Ultra-low-power RRAM-based FPGA: A Road towards Reconfigurable Edge Computing,” GOMACTech, 25-28 March 2019, Albuquerque, NM, USA. Published, 03/2019.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “FPGA-SPICE: A Simulation-based Architecture Evaluation Framework for FPGAs,” IEEE Transactions on Very Large Scale Integration Systems, vol. 27, no. 3, pp. 637-650, March 2019. Ranked within the IEEE TVLSI Top-10 popular articles from February to August May 2019.. Published, 03/2019.
  • P. Cadareanu, N. Reddy C, C. G. Almudever, A. Khanna, A. Parihar, A. Raychowdhury, S., K.Bertels, V. Narayanan, M. Di Ventra P.-E. Gaillardon, "Rebooting Our Computing Models," Design, Automation and Test in Europe (DATE), Invited Paper, 25-29 March 2019, Florence, Italy. Published, 03/2019.
  • E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P.-E. Gaillardon, G. De Micheli, "Scalable Boolean Methods In A Modern Synthesis Flow," Proceedings of the Design, Automation, and Test in Europe (DATE), 25-29 March 2019, Florence, Italy. Published, 03/2019.
  • E. Giacomin, T. Greenberg-Toledo, S. Kvatinsky, P.-E. Gaillardon, “A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications,” IEEETransactions on Circuits and Systems - I, vol. 66, bo. 2, pp. 643-654, February 2019. Published, 02/2019.
  • J. Romero Gonzalez, P.-E. Gaillardon, “BCB Benchmarking for Three-Independent-Gate Field Transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 221-254, 2018. Published, 12/2018.
  • O. Zografos, P.-E. Gaillardon, G. De Micheli, “Physical design of polarity controllable transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 189-220, 2018. Published, 12/2018.
  • X. Tang, P.-E. Gaillardon, I. O’Connor, G. De Micheli, “Ultrafine grain FPGAs with Polarity controllable Transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 273-298, 2018. Published, 12/2018.
  • L. Amaru, P.-E. Gaillardon, S. Mitra, G. De Micheli, “Exploratory Logic Synthesis for Multiple Independent Gate FETs,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 255-272, 2018. Published, 12/2018.
  • G. V. Resta, I. P. Radu, G. De Micheli, P.-E. Gaillardon, “WSe2 polarity-controllable devices,” Functionality- Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 71-90, 2018. Published, 12/2018.
  • M. Hasan, R. Walker, P.-E. Gaillardon, B. Sensale-Rodriquez, “Super Sensitive Terahertz Detectors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 129-146, 2018. Published, 12/2018.
  • J. Romero Gonzalez, P.-E. Gaillardon, “Three-Independent Gate FET’s Super Steep Subthreshold Slope,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 107-128, 2018. Published, 12/2018.
  • A. Levisse, P.-E. Gaillardon, B. Giraud, I. O'Connor, J. P. Noel, M. Moreau, J. M. Portal, "Resistive Switching Memory Architecture Based on Polarity Controllable Selectors," IEEE Transactions on Nanotechnology.Accepted for publication. Published, 12/2018.
  • P.-E. Gaillardon, “Functionality-Enhanced Devices: An alternative to Moore’s Law,” Edited Book, The Institution of Engineering and Technology, ISBN 978-1-78561-558-0, 10 December 2018. Published, 12/2018.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “FPGA-SPICE: A Simulation-based Architecture Evaluation Framework for FPGAs,” IEEE Transactions on Very Large Scale Integration Systems. Accepted for publication. Published, 12/2018.
  • J. Romero-Gonzalez, P.-E. Gaillardon, “An Efficient Adder Architecture with Three-Independent-Gate Field- Effect-Transistors,” IEEE International Conference on Rebooting Computing, 7-9 November 2018, Tysons, VA, USA. Published, 11/2018.
  • S. Rai, S. Srinivasa, P. Cadareanu, X. Yin, X. Sharon Hu, P.-E. Gaillardon, V. Narayanan, A. Kumar, "Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics?," IEEE 2018 International Conference On Computer Aided Design, 5-8 November 2018, San Diego, CA, USA, Invited paper. Published, 11/2018.
  • E. Giacomin, P.-E. Gaillardon, “A Resistive Random Access Memory Addon for the NCSU FreePDK 45nm,” IEEE Transactions on Nanotechnology, vol. 18, no. 1, pp. 68-72, November 2018. Published, 11/2018.
  • E. Giacomin, T. Greenberg-Toledo, S. Kvatinsky, P.-E. Gaillardon, “A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications,” IEEE Transactions on Circuits and Systems - I, Accepted for publication. Published, 11/2018.
  • E. Giacomin, P.-E. Gaillardon, “Differential Power Analysis Mitigation Technique Using Three-Independent- Gate Field Effect Transistors,” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI- SoC), 8-10 October 2018, Verona, Italy. Published, 10/2018.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “Post-P&R Performance and Power Analysis for RRAM-based FPGAs,”IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 639-650, Sept. 2018. Published, 09/2018.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler (2018). Logic Synthesis for RRAM-based In-Memory Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Published, 07/2018.
  • K. Le, A. Butterfield, K. Kelly, P.-E. Gaillardon, K. Tingey, T. Becnel, “Building Air Quality Sensors and Inspiring Citizen Scientists,” Chemical Engineering Education, vol. 52, no. 3, pp. 193-201, June 2018. Published, 06/2018.
  • G. V. Resta, Y. Balaji, D. Lin, I. P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, “Doping-free complementary inverter enabled by 2D WSe2 electrostatically- doped reconfigurable transistors,” 76th Device Research Conference, 24-27 June 2018, Santa Barbara, CA, USA. Published, 06/2018.
  • A. Butterfield, K. My Quyen, K. Kelly, P. Goffin, T. Becnel, P.-E. Gaillardon, "Citizen Scientists Engagement in Air Quality Measurements," 2018 ASEE Annual Conference & Exposition, 24-27 June 2018, Salt Lake City, UT, USA. Published, 06/2018.
  • J. Romero Gonzalez, P.-E. Gaillardon, “BCB Evaluation of High-Performance and Low-Leakage Three- Independent-Gate Field Effect Transistors”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 4, no. 1, pp. 1-9, June 2018. Published, 06/2018.
  • G. Resta, Y. Balaji, D. Lin, I. P. Radu F. Catthoor, P.-E. Gaillardon, G. De Micheli, “Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors,” ACS Nano, vol. 12, no. 7, pp. 7039-7047, July 2018. Published, 06/2018.
  • N. Talati, R. Ben Hur, A. Haj Ali, N. Wald, R. Ronen, P.-E. Gaillardon, S. Kvatinsky (2018). Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines. Design, Automation & Test in Europe Conference (DATE). Published, 03/2018.
  • G. V. Resta, J. Romero Gonzalez, Y. Balaji, T. Kumar Agarwal, D. Lin, F. Catthoor, G. De Micheli & I. P. Radu, P.-E. Gaillardon (2018). Towards High-Performance Polarity-Controllable FETs with 2D Materials. Design, Automation & Test in Europe Conference (DATE). Published, 03/2018.
  • T.-H. Lin, T. Margossian, L.-Q. Zheng, S. Kumar, I. Morozau, O. Sereda, D. Zemlyanov, C.-J. Shih, R. Zenobi, D. Baudouin, G. De Micheli, P.-E. Gaillardon, C. Copéret, “Conformal Deposition of Conductive Single- Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach”, Chemistry of Materials, vol. 30, no. 6, pp. 2168-2173, March 2018. Published, 03/2018.
  • A. Biscontini, M. Thammasack, G. De Micheli, P.-E. Gaillardon (2018). An FPGA-Based Test System for RRAM Technology Characterization. IEEE Transactions on Nanotechnologies. Published, 01/2018.
  • M. Thammasack, G. De Micheli, P.-E. Gaillardon, “Effect of O2- migration in Pt/HfO2/Ti/Pt structure,” Journal of Electroceramics,. Published, 12/2017.
  • L. Amaru, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, J. Olson, R. Brayton, G. D (2017). Enabling Exact Delay Synthesis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Published, 11/2017.
  • J. Reuben, R. Ben Hur, N. Wald, N. Talati, P.-E. Gaillardon, S. Kvatinsky (2017). Memristive Logic: A Framework for Evaluation and Comparison. 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Published, 09/2017.
  • E. Giacomin, J. Romero G., P.-E. Gaillardon (2017). Low-Power Multiplexer Designs Using Three-Independent-Gate Field Effect Transistors. IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch. Published, 07/2017.
  • M. Soeken, P.-E. Gaillardon, S. Shirinzadeh, R. Drechsler, G. De Micheli (2017). A PLiM Computer for the IoT. Computer Magazine. Published, 06/2017.
  • G. Meuli, M. Soeken, P.-E. Gaillardon, G. De Micheli (2017). A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing. IEEE ACM 26th International Workshop on Logic & Synthesis (IWLS). Published, 06/2017.
  • M. Nataraj, A. Levisse, B. Giraud, J.-P. Noel, P. Meinerzhagen, J.M. Portal, P.-E. Gaillardon, “Design Methodology for Area and Energy Efficient OxRAM-Based Non-Volatile Flip-Flop,” IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA,. Published, 05/2017.
  • M. Soeken, P.-E. Gaillardon, G. De Micheli, “RM3 Based Logic Synthesis,” Invited, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA. Published, 05/2017.
  • X. Tang, G. Kim, P.-E. Gaillardon, G. De Micheli, “A Study on the Programming Structures for RRAM-Based FPGA Architectures,” TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA. Published, 05/2017.
  • E. Giacomin, X. Tang, G. De Micheli, P.-E. Gaillardon, “Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(Ram) Programming Structure,” TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA. Published, 05/2017.
  • I. Tzouvadaki, S. Naus, P.-E. Gaillardon, A. Biscontini, G. De Micheli, S. Carrara, “An Efficient Electronic Measurement Interface for Memristive Biosensors,” IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA,. Published, 05/2017.
  • Z. Chu, X. Tang, M. Soeken, A. Petkovska, G. Zgheib, L. Amarú, Y. Xia, P. Ienne, G. De Micheli, P.-E. Gaillardon, “Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains,” 27th Great Lakes Symposium on VLSI (GLSVLSI), 10-12 May 2017, Banff, Alberta, Canada. Published, 05/2017.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “Physical Design Considerations of One-level RRAM-based Routing Multiplexers,” International Symposium on Physical Design (ISPD), 19-22 March 2017, Portland, OR, USA. Published, 03/2017.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, G. De Micheli, R. Drechsler, “Endurance Management for Resistive Logic-In-Memory Computing Architectures,” Design, Automation & Test in Europe Conference (DATE), 27-31 March 2017, Lausanne, Switzerland. Published, 03/2017.
  • G. Resta, T. Agarwal, D. Linn, F. Catthoor, P.-E. Gaillardon, G. De Micheli (2017). Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs. Nature Scientific Reports. Published, 03/2017.
  • X. Tang, G. De Micheli, P.-E. Gaillardon, “Optimization Opportunities in RRAM-based FPGA Architectures,” IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 20-23 February 2017, Bariloche, Argentina. Published, 02/2017.
  • W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “A Novel Basis for Logic Rewriting,” 22nd Asia and South Pacific Design Automation Conference ASP-DAC, 16-19 January 2017, Chiba, Japan. Published, 01/2017.
  • L. Amarú, M. Soeken, W. Haaswijk, E. Testa, P. Vuillod, J. Luo, P.-E. Gaillardon, G. De Micheli, “Multi-level Logic Benchmarks: An Exactness Study,” 22nd Asia and South Pacific Design Automation Conference ASP-DAC, 16-19 January 2017, Chiba, Japan. Published, 01/2017.
  • H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 12, pp. 1995-2007, December 2016. Published, 12/2016.
  • H. Ghasemzadeh, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M. Sonza Reorda, “A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors,” ACM Journal on Emerging Technologies in Computing Systems, vol 13, no. 2, pp. 16:1-16:13, November 2016. Published, 11/2016.
  • M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, “Perspectives of Multiple-Independent-Gate Field Effect Transistors for Efficient Terahertz Detection Applications,” SPIE Terahertz Emitters, Receivers, and Applications VII, 28 August-1 September 2016, San Francisco, CA, USA. Published, 09/2016.
  • G. V. Resta, S. Sutar, Y. Balaji, D. Lin, P. Raghavan, I. Radu, F. Catthoor, A. Thean, P.-E. Gaillardon, G. De Micheli, “Polarity control in WSe2,” Scientific Reports, 6:29448, July 2016. Published, 07/2016.
  • E. Testa, M. Soeken, O. Zografos, L. Amarú, P. Raghavan, R. Lauwereins, P.-E. Gaillardon, G. De Micheli, “Inversion Optimization in Majority-Inverter Graphs,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 18-20 July 2016, Beijing, China. Published, 07/2016.
  • M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, “A Compact DC Model for Dual-Independent-Gate FinFETs,” 74rd annual Device Research Conference, 19-22 June 2016, Newark, DE, USA. Published, 06/2016.
  • Y. Bi, K. Shamsi, J.-S. Yuan, P.-E. Gaillardon, G. De Micheli, X. Yin, X. S. Hu, M. Niemier, Y. Jin, “Emerging Technology based Design of Primitives for Hardware Security,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 1, pp. 3:1-3:19, June 2016. Published, 06/2016.
  • M. Soeken, S. Shririnzadeh, P.-E. Gaillardon, L. Amarú, R. Drechsler, G. De Micheli, " An MIG-based Compiler for Programmable Logic-in-Memory Architectures,” 53rd Design Automation Conference (DAC), 5-9 June 2016, Austin, TX, USA. Published, 06/2016.
  • W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “LUT Mapping and Optimization for Majority-Inverter Graphs,” 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA. Published, 06/2016.
  • E. Testa, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “Inversion Minimization in Majority-Inverter Graphs,” 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA. Published, 06/2016.
  • L. Amarú, P.-E. Gaillardon, G. De Micheli, “Majority-Inverter Graph: A New Paradigm for Logic Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 5, pp. 806-819, May 2016. Ranked within the IEEE TCAD Top-10 popular articles in May, June, July, August and September 2016.. Published, 05/2016.
  • A. Chattopadhyay, L. Amarú, M. Soeken, P.-E. Gaillardon, G. De Micheli, “Notes on Majority Boolean Algebra,” IEEE International Symposium on Multi-Valued Logic (ISMVL), 18-20 May 2016. Published, 05/2016.
  • P.-E. Gaillardon, M. Hasan, A. Saha, L. Amarú, R. Walker, B. Sensale-Rodriguez, “Digital, Analog and RF Design Opportunities of Three-Independent-Gate Transistors,” Invited, IEEE International Symposium on Circuits and Systems (ISCAS), 22-25 May 2016, Montreal, Canada. Published, 05/2016.
  • J. Sandrini, M. Barlas, M. Thammasack, T. Demirci, M. De Marchi, D. Sacchetto, P.-E. Gaillardon, G. De Micheli, Y. Leblebici, “Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 339-351, April 2016. Published, 04/2016.
  • P.-E. Gaillardon, R. Magni, L. Amarú, M. Hasan, R. Walker, B. Sensale-Rodriguez, J.-F. Christmann, E. Beigné, “Three-Independent-Gate Transistors: Opportunities in Digital, Analog and RF Applications,” Invited, IEEE Latin-American Test Symposium (LATS), 6-8 April 2016, Foz de Iguaçu, Brazil. Published, 04/2016.
  • P.-E. Gaillardon, R. Walker, B. Sensale-Rodriguez, “Breakthroughs in Analog and RF Circuit Performance through Steep-Slope FinFETs,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA. Published, 03/2016.
  • L. Amarú, P.-E. Gaillardon, R. Wille, G. De Micheli, “Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “Optimizing Majority-Inverter Graphs With Functional Hashing,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • K. Shamsi, P.-E. Gaillardon, Y. Jin, “Hardware Platform Protection Using Emerging Memory Technologies,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA. Published, 03/2016.
  • P.-E. Gaillardon, L. Amarú, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, “The PLiM Computer: Computing within a Resistive Memory Array,” Invited, Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, “Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • X. Tang, P.-E. Gaillardon, G. De Micheli, “A Full-Capacity Local Routing Architecture for FPGAs,” Abstract, 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 21-23 February 2016, Monterey, CA, USA. Published, 02/2016.
  • L. Amarú, P.-E. Gaillardon, G. De Micheli, “Majority-based Synthesis for Nanotechnologies,” Invited, 21st Asia and South Pacific Design Automation Conference ASP-DAC, 25-28 January 2016, Macao, China. Published, 01/2016.
  • A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli, “Computationally Efficient Multiple-Independent-Gate Device Model,” IEEE Transactions on Nanotechnology, vol. 15, no. 1, pp. 2-14, January 2016. Published, 01/2016.
  • . Vana, P.-E. Gaillardon, A. Teman, “C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors,” IEEE Transactions on Nanotechnology, vol. 19, no. 1, pp. 123-136, January 2020. Published, 01/2010.

Presentations

  • P.-E. Gaillardon, “OpenFPGA: Bringing Open-source Hardware to FPGAs," 17-19 April 2023, Design, Automation & Test in Europe Conference (DATE), Antwerp, Belgium. Invited Talk/Keynote, Presented, 04/2023.
  • P.-E. Gaillardon, “Is In-Memory computing a niche area or the main hardware platform for AI/ML?,” 20-21 April 2023, Symposium on “Emerging Technologies and Applications”, Montreux, Switzerland. Invited Talk/Keynote, Presented, 03/2023.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA," 31st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 13-14 February 2023, Monterey, CA, USA. Tutorial . Invited Talk/Keynote, Presented, 02/2023.
  • P.-E. Gaillardon, “Open-source and FPGAs: Hardware, Software, Both or None?," 31st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 13-14 February 2023, Monterey, CA, USA. Panel . Invited Talk/Keynote, Presented, 02/2023.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA," 20th International Conference on Field Programmable Technology (FPT), 5-9 December 2022, Hong Kong, China Tutorial . Invited Talk/Keynote, Presented, 12/2022.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 7-9 December 2022, virtual. Keynote . Invited Talk/Keynote, Presented, 12/2022.
  • P.-E. Gaillardon, “Under the Hood of LSOracle and OpenFPGA,” Samsung, 6 June 2022, Korean. Invited Talk/Keynote, Presented, 06/2022.
  • P.-E. Gaillardon, “Introduction to OpenFPGA (Philopsophy, Capabilities, Directions)," 31st IEEE International Symposium On Field-Programmable Custom Computing Machines, 8-11 May 2022, Los Angeles, USA. Tutorial . Invited Talk/Keynote, Presented, 05/2022.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA," IEEE 14th Latin American Symposium on Circuits & Systems (LASCAS), 1-4 March 2022, Puerto Varas, Chile Keynote . Invited Talk/Keynote, Presented, 03/2022.
  • P.-E. Gaillardon, “Heterogeneous 3D Integration," IEEE 14th Latin American Symposium on Circuits & Systems (LASCAS), 1-4 March 2022, Puerto Varas, Chile Panel . Invited Talk/Keynote, Presented, 01/2022.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA,” 3rd Workshop on Accelerator Computer Aided Design (ACCAD 2021) Co-located with ICCAD 2021, 4-5 November 2021, Virtual. Invited Talk/Keynote, Presented, 11/2021.
  • P.-E. Gaillardon, “OpenFPGA: From POSH/IDEA to the Open-Source FPGA Foundation,” The Future of Open-Source Chip Design Tools – DARPA Electronics Resurgence Initiative 2021, 20 October 2021, Virtual. Invited Talk/Keynote, Presented, 10/2021.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA,” IEEE CASS – Youtube Live, 17 September 2021, Virtual. Invited Talk/Keynote, Presented, 09/2021.
  • P.-E. Gaillardon, “Learning-based Techniques for Automatic Logic Optimization,” 30th International Workshop on Logic & Synthesis (IWLS), 19-22 July 2021, Virtual. Invited Talk/Keynote, Presented, 07/2021.
  • P.-E. Gaillardon, “Under the Hood of LSOracle,” Logic Synthesis Software School 2.0, 23 June 2021, Virtual. Invited Talk/Keynote, Presented, 06/2021.
  • P.-E. Gaillardon, “A Scalable and Robust Hierarchical Framework to Enable 24-hour Prototyping for 100k-LUT FPGAs,” Xilinx Tech. Talks, Xilinx Inc., 7 May 2021, San Jose, CA, USA. Invited Talk/Keynote, Presented, 05/2021.
  • P.-E. Gaillardon, “Introduction to OpenFPGA: An Open-source FPGA IP Generator,” The Open-source FPGA Foundation, 14 May 2021, webinar. Invited Talk/Keynote, Presented, 05/2021.
  • P.-E. Gaillardon, “Introduction to OpenFPGA: An Open-source FPGA IP Generator,” The Open-source FPGA Foundation, 14 May 2021, webinar. Invited Talk/Keynote, Presented, 05/2021.
  • P.-E. Gaillardon, “Under the Hood of OpenFPGA,” Open-source Hardware and EDA seminar series, University of California Santa Cruz, 20 April 2021, Santa Cruz, CA, USA. Invited Talk/Keynote, Presented, 04/2021.
  • P.-E. Gaillardon, “Under the Hood of LSOracle and OpenFPGA,” AMD Research Inc., 26 March 2021, Austin, TX, USA. Invited Talk/Keynote, Presented, 03/2021.
  • P.-E. Gaillardon, “Under the Hood of LSOracle and OpenFPGA,” Synopsys, Inc., 26 February 2021, Santa Clara, CA, USA. Invited Talk/Keynote, Presented, 02/2021.
  • P.-E. Gaillardon, “OpenFPGA: Automate the Design of Customizable FPGAs,” DARPA Electronics Resurgence Initiative Summit 2020, 18 August 2020, virtual. Invited Talk/Keynote, Presented, 08/2020.
  • P.-E. Gaillardon, “Open-source EDA innovations: From Traditional Systems to Emerging Technologies,” Emerging Technologies for EDA Workshop organized by the Ministry of Science and Technology (MOST), 21 March 2019, Hsinchu, Taiwan. Invited Talk/Keynote, Presented, 03/2019.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Department of Electrical Engineering, 16 May 2018, KU Leuven, Leuven, BE. Invited Talk/Keynote, Presented, 05/2018.
  • P.-E. Gaillardon, “Emerging Technologies for Computing---From Devices to Systems,” 19 March 2018, DATE conference, Dresden, Germany. Tutorial . Invited Talk/Keynote, Accepted, 03/2018.
  • P.-E. Gaillardon, “Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors,” "Beyond CMOS” ESSDERC tutorial, 11 September 2017, Leuven, Belgium. Tutorial. Invited Talk/Keynote, Presented, 11/2017.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Lyon Institute of Nanotechnologies, 30 November 2017, Ecole Centrale de Lyon, Lyon, FR. Invited Talk/Keynote, Presented, 11/2017.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Department of Electrical and Computer Engineering, 25 October 2017, Brigham Young University, Provo, UT, USA. Invited Talk/Keynote, Presented, 10/2017.
  • P.-E. Gaillardon, “Towards Functionality-Enhanced Devices: An Alternative to Moore's Law,” EPFL Workshop on Logic Synthesis & Emerging Technologies, 28-29 September 2017, Lausanne, Switzerland. Invited Talk/Keynote, Presented, 09/2017.
  • P.-E. Gaillardon, “Towards Lower-Power High-Performance FPGAs with RRAM-based Routing,” Stephen and Sharon Seiden Workshop on Beyond CMOS: From Devices to Systems workshop, 5-6 June 2017, Technion, Haifa, Israel. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “In-memory Computing with Majority RRAM Operations,” 9th 3D Silicon Integration Workshop (D43D), 27 June 2017, Grenoble, France. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “Opportunities of Resistive Back-End Memories: From Technology to Reconfigurable Logic,” Third MemoCIS Training School, 7-9 June 2017, Technion, Haifa, Israel. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “Neuromorphic Computing and Deep Learning,” 19th ACM/IEEE System Level Interconnect Prediction (SLIP), 17 June 2017, Austin, TX, USA. Panel. Other, Presented, 06/2017.
  • P.-E. Gaillardon, "Nano-Tera.ch - Next 1000x Gains: from Clouds to IoT Systems," 26 March 2017, DATE conference, Lausanne, Switzerland. Tutorial . Invited Talk/Keynote, Presented, 03/2017.

Research Groups

  • Skylar Stockham, Undergraduate Student. 11/2022 - present.
  • Raven Reitstetter, Senior Associate. 03/2022 - present.
  • Olivia Lam, Undergraduate Student. 01/2022 - 12/2022.
  • Owen Leishman, Undergraduate Student. 08/2021 - present.
  • Daniel Wakeham, Graduate Student. 08/2021 - 12/2022.
  • Michael Keyser, Undergraduate Student. 07/2021 - 12/2022.
  • Allen Boston, Graduate Student. 06/2021 - present.
  • Andrew Erikson, Undergraduate Student. 05/2021 - 08/2021.
  • Nichols Crawford Taylor, Undergraduate Student. 05/2021 - 08/2021.
  • Dillon Lee, Senior Associate. 03/01/2021 - 05/01/2021.
  • Roman Gauchi, Postdoc. 03/2021 - 12/2022.
  • Hugo Maitre, Visiting Student. 03/2021 - 07/2021.
  • Léa Enginger, Visiting Student. 03/2021 - 09/2021.
  • Faris Kahn, Undergraduate Student. 01/2021 - 05/2021.
  • Andrew Pond, Graduate Student. 01/2021 - 12/2021.
  • Will Ransohoff, Other. 01/2021 - 05/2021.
  • Clara Chevreau, Senior Associate. 01/2021 - 09/2022.
  • Benjamin Leaptrop, Undergraduate Student. 01/2021 - 10/2021.
  • Corinne Garcia, Senior Associate. 12/2020 - present.
  • Ashton Snelgrove, Graduate Student. 11/2020 - present.
  • Grant Brown, Graduate Student. 08/2020 - 08/2023.
  • Clement Cazaban, Visiting Student. 07/2020 - 05/2021.
  • Nathan Page, Graduate Student. 05/2020 - 04/2022.
  • Virgile Colrat, Visiting Student. 03/2020 - 11/2020.
  • Samy Charas, Visiting Student. 03/2020 - 08/2020.
  • Valerio Tenace, Postdoc. 11/2019 - 07/2021.
  • Henry Gilbert, Undergraduate Student. 05/2019 - 08/2020.
  • Scott Temple, Senior Associate. 05/2019 - 12/2022.
  • Quang Nguyen, Graduate Student. 05/2019 - 05/2020.
  • Matthieu Couriol, Graduate Student. 04/2019 - 09/2023.
  • Ganesh Gore, Graduate Student. 01/2019 - 02/2023.
  • Scott Gale, Graduate Student. 01/2019 - 05/2020.
  • Amitesh Kumar, Postdoc. 01/2019 - 08/2019.
  • Joao Vieira, Graduate Student. 01/2019 - 08/2019.
  • Baudouin Chauviere, Graduate Student. 09/2018 - 05/2020.
  • Aurelien Alacchi, Graduate Student. 09/2018 - 10/2022.
  • Patsy Cadareanu, Graduate Student. 08/2018 - present.
  • Harikrishna Kambala, Graduate Student. 08/2018 - 12/2018.
  • Walter Lau, Graduate Student. 08/2018 - 05/2022.
  • Max Austin, Graduate Student. 07/2018 - 11/2020.
  • Trenton Taylor, Undergraduate Student. 05/2018 - 05/2019.
  • Xifan Tang, Postdoc. 04/2018 - 07/2021.
  • Devin Renshaw, Graduate Student. 08/2017 - 06/2018.
  • Edouard Giacomin, Graduate Student. 01/2017 - 05/2021.
  • Tom Becnel, Graduate Student. 01/2017 - 05/2022.
  • Jorge Romero, Graduate Student. 08/2016 - 05/2018.

Software Titles

  • OpenFPGA. The world-first open-source FPGA IP. Release Date: 06/2022.
  • LSOracle. An oracle-based Logic Synthesis framework. Release Date: 06/2022.
  • FPGA-SPICE. Tool to evaluate the electrical performance of advanced FPGAs. Release Date: 03/2018.