PIERRE-EMMANUEL GAILLARDON portrait
  • Adjunct Assistant Professor, School Of Computing
  • Assistant Professor, Elect & Computer Engineering

Publications

  • P. Cadareanu, N. Reddy C, C. G. Almudever, A. Khanna, A. Parihar, A. Raychowdhury, S., K.Bertels, V. Narayanan, M. Di Ventra P.-E. Gaillardon, "Rebooting Our Computing Models," Design, Automation and Test in Europe (DATE), Invited Paper, 25-29 March 2019, Florence, Italy. Published, 03/2019.
  • E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P.-E. Gaillardon, G. De Micheli, "Scalable Boolean Methods In A Modern Synthesis Flow," Proceedings of the Design, Automation, and Test in Europe (DATE), 25-29 March 2019, Florence, Italy. Published, 03/2019.
  • J. Romero Gonzalez, P.-E. Gaillardon, “BCB Benchmarking for Three-Independent-Gate Field Transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 221-254, 2018. Published, 12/2018.
  • O. Zografos, P.-E. Gaillardon, G. De Micheli, “Physical design of polarity controllable transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 189-220, 2018. Published, 12/2018.
  • X. Tang, P.-E. Gaillardon, I. O’Connor, G. De Micheli, “Ultrafine grain FPGAs with Polarity controllable Transistors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 273-298, 2018. Published, 12/2018.
  • L. Amaru, P.-E. Gaillardon, S. Mitra, G. De Micheli, “Exploratory Logic Synthesis for Multiple Independent Gate FETs,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 255-272, 2018. Published, 12/2018.
  • G. V. Resta, I. P. Radu, G. De Micheli, P.-E. Gaillardon, “WSe2 polarity-controllable devices,” Functionality- Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 71-90, 2018. Published, 12/2018.
  • M. Hasan, R. Walker, P.-E. Gaillardon, B. Sensale-Rodriquez, “Super Sensitive Terahertz Detectors,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 129-146, 2018. Published, 12/2018.
  • J. Romero Gonzalez, P.-E. Gaillardon, “Three-Independent Gate FET’s Super Steep Subthreshold Slope,” Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 107-128, 2018. Published, 12/2018.
  • A. Levisse, P.-E. Gaillardon, B. Giraud, I. O'Connor, J. P. Noel, M. Moreau, J. M. Portal, "Resistive Switching Memory Architecture Based on Polarity Controllable Selectors," IEEE Transactions on Nanotechnology.Accepted for publication. Published, 12/2018.
  • P.-E. Gaillardon, “Functionality-Enhanced Devices: An alternative to Moore’s Law,” Edited Book, The Institution of Engineering and Technology, ISBN 978-1-78561-558-0, 10 December 2018. Published, 12/2018.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “FPGA-SPICE: A Simulation-based Architecture Evaluation Framework for FPGAs,” IEEE Transactions on Very Large Scale Integration Systems. Accepted for publication. Published, 12/2018.
  • J. Romero-Gonzalez, P.-E. Gaillardon, “An Efficient Adder Architecture with Three-Independent-Gate Field- Effect-Transistors,” IEEE International Conference on Rebooting Computing, 7-9 November 2018, Tysons, VA, USA. Published, 11/2018.
  • S. Rai, S. Srinivasa, P. Cadareanu, X. Yin, X. Sharon Hu, P.-E. Gaillardon, V. Narayanan, A. Kumar, "Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics?," IEEE 2018 International Conference On Computer Aided Design, 5-8 November 2018, San Diego, CA, USA, Invited paper. Published, 11/2018.
  • E. Giacomin, P.-E. Gaillardon, “A Resistive Random Access Memory Addon for the NCSU FreePDK 45nm,” IEEE Transactions on Nanotechnology, vol. 18, no. 1, pp. 68-72, November 2018. Published, 11/2018.
  • E. Giacomin, T. Greenberg-Toledo, S. Kvatinsky, P.-E. Gaillardon, “A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications,” IEEE Transactions on Circuits and Systems - I, Accepted for publication. Published, 11/2018.
  • E. Giacomin, P.-E. Gaillardon, “Differential Power Analysis Mitigation Technique Using Three-Independent- Gate Field Effect Transistors,” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI- SoC), 8-10 October 2018, Verona, Italy. Published, 10/2018.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “Post-P&R Performance and Power Analysis for RRAM-based FPGAs,”IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 639-650, Sept. 2018. Published, 09/2018.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler (2018). Logic Synthesis for RRAM-based In-Memory Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Published, 07/2018.
  • K. Le, A. Butterfield, K. Kelly, P.-E. Gaillardon, K. Tingey, T. Becnel, “Building Air Quality Sensors and Inspiring Citizen Scientists,” Chemical Engineering Education, vol. 52, no. 3, pp. 193-201, June 2018. Published, 06/2018.
  • G. V. Resta, Y. Balaji, D. Lin, I. P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, “Doping-free complementary inverter enabled by 2D WSe2 electrostatically- doped reconfigurable transistors,” 76th Device Research Conference, 24-27 June 2018, Santa Barbara, CA, USA. Published, 06/2018.
  • A. Butterfield, K. My Quyen, K. Kelly, P. Goffin, T. Becnel, P.-E. Gaillardon, "Citizen Scientists Engagement in Air Quality Measurements," 2018 ASEE Annual Conference & Exposition, 24-27 June 2018, Salt Lake City, UT, USA. Published, 06/2018.
  • J. Romero Gonzalez, P.-E. Gaillardon, “BCB Evaluation of High-Performance and Low-Leakage Three- Independent-Gate Field Effect Transistors”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 4, no. 1, pp. 1-9, June 2018. Published, 06/2018.
  • G. Resta, Y. Balaji, D. Lin, I. P. Radu F. Catthoor, P.-E. Gaillardon, G. De Micheli, “Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors,” ACS Nano, vol. 12, no. 7, pp. 7039-7047, July 2018. Published, 06/2018.
  • N. Talati, R. Ben Hur, A. Haj Ali, N. Wald, R. Ronen, P.-E. Gaillardon, S. Kvatinsky (2018). Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines. Design, Automation & Test in Europe Conference (DATE). Published, 03/2018.
  • G. V. Resta, J. Romero Gonzalez, Y. Balaji, T. Kumar Agarwal, D. Lin, F. Catthoor, G. De Micheli & I. P. Radu, P.-E. Gaillardon (2018). Towards High-Performance Polarity-Controllable FETs with 2D Materials. Design, Automation & Test in Europe Conference (DATE). Published, 03/2018.
  • T.-H. Lin, T. Margossian, L.-Q. Zheng, S. Kumar, I. Morozau, O. Sereda, D. Zemlyanov, C.-J. Shih, R. Zenobi, D. Baudouin, G. De Micheli, P.-E. Gaillardon, C. Copéret, “Conformal Deposition of Conductive Single- Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach”, Chemistry of Materials, vol. 30, no. 6, pp. 2168-2173, March 2018. Published, 03/2018.
  • A. Biscontini, M. Thammasack, G. De Micheli, P.-E. Gaillardon (2018). An FPGA-Based Test System for RRAM Technology Characterization. IEEE Transactions on Nanotechnologies. Published, 01/2018.
  • M. Thammasack, G. De Micheli, P.-E. Gaillardon, “Effect of O2- migration in Pt/HfO2/Ti/Pt structure,” Journal of Electroceramics,. Published, 12/2017.
  • L. Amaru, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, J. Olson, R. Brayton, G. D (2017). Enabling Exact Delay Synthesis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Published, 11/2017.
  • J. Reuben, R. Ben Hur, N. Wald, N. Talati, P.-E. Gaillardon, S. Kvatinsky (2017). Memristive Logic: A Framework for Evaluation and Comparison. 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Published, 09/2017.
  • E. Giacomin, J. Romero G., P.-E. Gaillardon (2017). Low-Power Multiplexer Designs Using Three-Independent-Gate Field Effect Transistors. IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch. Published, 07/2017.
  • M. Soeken, P.-E. Gaillardon, S. Shirinzadeh, R. Drechsler, G. De Micheli (2017). A PLiM Computer for the IoT. Computer Magazine. Published, 06/2017.
  • G. Meuli, M. Soeken, P.-E. Gaillardon, G. De Micheli (2017). A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing. IEEE ACM 26th International Workshop on Logic & Synthesis (IWLS). Published, 06/2017.
  • M. Nataraj, A. Levisse, B. Giraud, J.-P. Noel, P. Meinerzhagen, J.M. Portal, P.-E. Gaillardon, “Design Methodology for Area and Energy Efficient OxRAM-Based Non-Volatile Flip-Flop,” IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA,. Published, 05/2017.
  • M. Soeken, P.-E. Gaillardon, G. De Micheli, “RM3 Based Logic Synthesis,” Invited, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA. Published, 05/2017.
  • X. Tang, G. Kim, P.-E. Gaillardon, G. De Micheli, “A Study on the Programming Structures for RRAM-Based FPGA Architectures,” TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA. Published, 05/2017.
  • E. Giacomin, X. Tang, G. De Micheli, P.-E. Gaillardon, “Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(Ram) Programming Structure,” TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA. Published, 05/2017.
  • I. Tzouvadaki, S. Naus, P.-E. Gaillardon, A. Biscontini, G. De Micheli, S. Carrara, “An Efficient Electronic Measurement Interface for Memristive Biosensors,” IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA,. Published, 05/2017.
  • Z. Chu, X. Tang, M. Soeken, A. Petkovska, G. Zgheib, L. Amarú, Y. Xia, P. Ienne, G. De Micheli, P.-E. Gaillardon, “Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains,” 27th Great Lakes Symposium on VLSI (GLSVLSI), 10-12 May 2017, Banff, Alberta, Canada. Published, 05/2017.
  • G. Resta, T. Agarwal, D. Linn, F. Catthoor, P.-E. Gaillardon, G. De Micheli (2017). Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs. Nature Scientific Reports. Published, 03/2017.
  • X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, “Physical Design Considerations of One-level RRAM-based Routing Multiplexers,” International Symposium on Physical Design (ISPD), 19-22 March 2017, Portland, OR, USA. Published, 03/2017.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, G. De Micheli, R. Drechsler, “Endurance Management for Resistive Logic-In-Memory Computing Architectures,” Design, Automation & Test in Europe Conference (DATE), 27-31 March 2017, Lausanne, Switzerland. Published, 03/2017.
  • X. Tang, G. De Micheli, P.-E. Gaillardon, “Optimization Opportunities in RRAM-based FPGA Architectures,” IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 20-23 February 2017, Bariloche, Argentina. Published, 02/2017.
  • W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “A Novel Basis for Logic Rewriting,” 22nd Asia and South Pacific Design Automation Conference ASP-DAC, 16-19 January 2017, Chiba, Japan. Published, 01/2017.
  • L. Amarú, M. Soeken, W. Haaswijk, E. Testa, P. Vuillod, J. Luo, P.-E. Gaillardon, G. De Micheli, “Multi-level Logic Benchmarks: An Exactness Study,” 22nd Asia and South Pacific Design Automation Conference ASP-DAC, 16-19 January 2017, Chiba, Japan. Published, 01/2017.
  • H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, “Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 12, pp. 1995-2007, December 2016. Published, 12/2016.
  • H. Ghasemzadeh, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M. Sonza Reorda, “A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors,” ACM Journal on Emerging Technologies in Computing Systems, vol 13, no. 2, pp. 16:1-16:13, November 2016. Published, 11/2016.
  • M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, “Perspectives of Multiple-Independent-Gate Field Effect Transistors for Efficient Terahertz Detection Applications,” SPIE Terahertz Emitters, Receivers, and Applications VII, 28 August-1 September 2016, San Francisco, CA, USA. Published, 09/2016.
  • G. V. Resta, S. Sutar, Y. Balaji, D. Lin, P. Raghavan, I. Radu, F. Catthoor, A. Thean, P.-E. Gaillardon, G. De Micheli, “Polarity control in WSe2,” Scientific Reports, 6:29448, July 2016. Published, 07/2016.
  • E. Testa, M. Soeken, O. Zografos, L. Amarú, P. Raghavan, R. Lauwereins, P.-E. Gaillardon, G. De Micheli, “Inversion Optimization in Majority-Inverter Graphs,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 18-20 July 2016, Beijing, China. Published, 07/2016.
  • Y. Bi, K. Shamsi, J.-S. Yuan, P.-E. Gaillardon, G. De Micheli, X. Yin, X. S. Hu, M. Niemier, Y. Jin, “Emerging Technology based Design of Primitives for Hardware Security,” ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 1, pp. 3:1-3:19, June 2016. Published, 06/2016.
  • M. Soeken, S. Shririnzadeh, P.-E. Gaillardon, L. Amarú, R. Drechsler, G. De Micheli, " An MIG-based Compiler for Programmable Logic-in-Memory Architectures,” 53rd Design Automation Conference (DAC), 5-9 June 2016, Austin, TX, USA. Published, 06/2016.
  • W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “LUT Mapping and Optimization for Majority-Inverter Graphs,” 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA. Published, 06/2016.
  • E. Testa, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “Inversion Minimization in Majority-Inverter Graphs,” 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA. Published, 06/2016.
  • M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, “A Compact DC Model for Dual-Independent-Gate FinFETs,” 74rd annual Device Research Conference, 19-22 June 2016, Newark, DE, USA. Published, 06/2016.
  • L. Amarú, P.-E. Gaillardon, G. De Micheli, “Majority-Inverter Graph: A New Paradigm for Logic Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 5, pp. 806-819, May 2016. Ranked within the IEEE TCAD Top-10 popular articles in May, June, July, August and September 2016.. Published, 05/2016.
  • A. Chattopadhyay, L. Amarú, M. Soeken, P.-E. Gaillardon, G. De Micheli, “Notes on Majority Boolean Algebra,” IEEE International Symposium on Multi-Valued Logic (ISMVL), 18-20 May 2016. Published, 05/2016.
  • P.-E. Gaillardon, M. Hasan, A. Saha, L. Amarú, R. Walker, B. Sensale-Rodriguez, “Digital, Analog and RF Design Opportunities of Three-Independent-Gate Transistors,” Invited, IEEE International Symposium on Circuits and Systems (ISCAS), 22-25 May 2016, Montreal, Canada. Published, 05/2016.
  • J. Sandrini, M. Barlas, M. Thammasack, T. Demirci, M. De Marchi, D. Sacchetto, P.-E. Gaillardon, G. De Micheli, Y. Leblebici, “Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 339-351, April 2016. Published, 04/2016.
  • P.-E. Gaillardon, R. Magni, L. Amarú, M. Hasan, R. Walker, B. Sensale-Rodriguez, J.-F. Christmann, E. Beigné, “Three-Independent-Gate Transistors: Opportunities in Digital, Analog and RF Applications,” Invited, IEEE Latin-American Test Symposium (LATS), 6-8 April 2016, Foz de Iguaçu, Brazil. Published, 04/2016.
  • P.-E. Gaillardon, R. Walker, B. Sensale-Rodriguez, “Breakthroughs in Analog and RF Circuit Performance through Steep-Slope FinFETs,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA. Published, 03/2016.
  • L. Amarú, P.-E. Gaillardon, R. Wille, G. De Micheli, “Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, “Optimizing Majority-Inverter Graphs With Functional Hashing,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • K. Shamsi, P.-E. Gaillardon, Y. Jin, “Hardware Platform Protection Using Emerging Memory Technologies,” Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA. Published, 03/2016.
  • P.-E. Gaillardon, L. Amarú, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, “The PLiM Computer: Computing within a Resistive Memory Array,” Invited, Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, “Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs,” Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany. Published, 03/2016.
  • X. Tang, P.-E. Gaillardon, G. De Micheli, “A Full-Capacity Local Routing Architecture for FPGAs,” Abstract, 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 21-23 February 2016, Monterey, CA, USA. Published, 02/2016.
  • L. Amarú, P.-E. Gaillardon, G. De Micheli, “Majority-based Synthesis for Nanotechnologies,” Invited, 21st Asia and South Pacific Design Automation Conference ASP-DAC, 25-28 January 2016, Macao, China. Published, 01/2016.
  • A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli, “Computationally Efficient Multiple-Independent-Gate Device Model,” IEEE Transactions on Nanotechnology, vol. 15, no. 1, pp. 2-14, January 2016. Published, 01/2016.

Presentations

  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Department of Electrical Engineering, 16 May 2018, KU Leuven, Leuven, BE. Invited Talk/Keynote, Presented, 05/2018.
  • P.-E. Gaillardon, “Emerging Technologies for Computing---From Devices to Systems,” 19 March 2018, DATE conference, Dresden, Germany. Tutorial . Invited Talk/Keynote, Accepted, 03/2018.
  • P.-E. Gaillardon, “Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors,” "Beyond CMOS” ESSDERC tutorial, 11 September 2017, Leuven, Belgium. Tutorial. Invited Talk/Keynote, Presented, 11/2017.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Lyon Institute of Nanotechnologies, 30 November 2017, Ecole Centrale de Lyon, Lyon, FR. Invited Talk/Keynote, Presented, 11/2017.
  • P.-E. Gaillardon, “What about increasing the device functionality rather than scaling them?,” Department of Electrical and Computer Engineering, 25 October 2017, Brigham Young University, Provo, UT, USA. Invited Talk/Keynote, Presented, 10/2017.
  • P.-E. Gaillardon, “Towards Functionality-Enhanced Devices: An Alternative to Moore's Law,” EPFL Workshop on Logic Synthesis & Emerging Technologies, 28-29 September 2017, Lausanne, Switzerland. Invited Talk/Keynote, Presented, 09/2017.
  • P.-E. Gaillardon, “Towards Lower-Power High-Performance FPGAs with RRAM-based Routing,” Stephen and Sharon Seiden Workshop on Beyond CMOS: From Devices to Systems workshop, 5-6 June 2017, Technion, Haifa, Israel. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “In-memory Computing with Majority RRAM Operations,” 9th 3D Silicon Integration Workshop (D43D), 27 June 2017, Grenoble, France. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “Opportunities of Resistive Back-End Memories: From Technology to Reconfigurable Logic,” Third MemoCIS Training School, 7-9 June 2017, Technion, Haifa, Israel. Invited Talk/Keynote, Presented, 06/2017.
  • P.-E. Gaillardon, “Neuromorphic Computing and Deep Learning,” 19th ACM/IEEE System Level Interconnect Prediction (SLIP), 17 June 2017, Austin, TX, USA. Panel. Other, Presented, 06/2017.
  • P.-E. Gaillardon, "Nano-Tera.ch - Next 1000x Gains: from Clouds to IoT Systems," 26 March 2017, DATE conference, Lausanne, Switzerland. Tutorial . Invited Talk/Keynote, Presented, 03/2017.

Research Groups

  • Ganesh Gore, Graduate Student. 01/2019 - present.
  • Amitesh Kumar, Postdoc. 01/2019 - present.
  • Joao Vieira, Graduate Student. 01/2019 - present.
  • Baudouin Chauviere, Graduate Student. 09/2018 - present.
  • Aurelien Alacchi, Graduate Student. 09/2018 - present.
  • Patsy Cadareanu, Graduate Student. 08/2018 - present.
  • Harikrishna Kambala, Graduate Student. 08/2018 - 12/2018.
  • Walter Lau, Graduate Student. 08/2018 - present.
  • Max Austin, Graduate Student. 07/2018 - present.
  • Trenton Taylor, Undergraduate Student. 05/2018 - present.
  • Xifan Tang, Postdoc. 04/2018 - present.
  • Devin Renshaw, Graduate Student. 08/2017 - 06/2018.
  • Edouard Giacomin, Graduate Student. 01/2017 - present.
  • Tom Becnel, Graduate Student. 01/2017 - present.
  • Jorge Romero, Graduate Student. 08/2016 - 05/2018.

Software Titles

  • LSOracle. An oracle-based Logic Synthesis framework. Release Date: 12/2018.
  • OpenFPGA. The world-first open-source FPGA IP. Release Date: 09/2018.
  • FPGA-SPICE. Tool to evaluate the electrical performance of advanced FPGAs. Release Date: 03/2018.